A, B and C_in are the three inputs of a full adder circuit and D₀, D₁, ..., D₇ are the inputs of 8 ∶ 1 multiplexer. S₂ (MSB), S₁ and S₀ (LSB) are the selection lines of the multiplexer. To implement the expression of sum of full adder circuit using this multiplexer, the connections of the input ports and selection lines are

Full adder is a combinational logic circuit. A full adder has three inputs ( each of one bit ) termed as A, B and Cin that generates sum ( S ) and carry ( C ) in the output. A full adder circuit is designed using two AND gate, two XOR gate, and one OR gate. The XOR gate gives the output for sum and the OR gate gives the output for carry.

A MUX or a multiplexer is a digital logic circuit ( combinational circuit ). A multiplexer has many inputs and only one output. The output depends upon the input given to the select lines.

Truth table for full adder is shown below. This truth table is written by the concept of binary addition. That is

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0, carry = 1.

Now we will implement this full adder in 8:1 MUX for implementing sum: which gives 

D0 = D3 = D5 = D6 = 0, D1 = D2 = D4 = D7 = 1, S2 = A, S1 = B and S0 = Cin

 For sum:

For Carry:

Hence option 1 is correct