Synchronous Counters MCQ Quiz in தமிழ் - Objective Question with Answer for Synchronous Counters - இலவச PDF ஐப் பதிவிறக்கவும்

Concept:

For an ‘n’ flip flop counter,

• The total number of states = 2n (0 to 2n – 1)
• The largest number that can be stored in the counter = 2n – 1

To construct any mod counter, the minimum number flip flops required such that: Modulus ≤ 2n

Where n is the number of counters.

Calculation:

Number no. of flip – flops are required to construct a mod-10 counter (decade counter) is obtained as:

2n ≥ 10 i.e. n = 4

Concept:

For a MOD-n counter the output waveform frequency :

\({f_1} = \frac{{{f_{clk}}}}{n}\)

Calculation:

Let Mod P, Mod Q, and Mod R counter are connected in cascade. The resultant counter size will be:

Mod P × Q × R

∴ 5 × 10 × K = 750

\(K = \frac{{750}}{{50}} = 15\)

Concept:

For a counter with ‘n’ flip flops:

• The total number of states = 2n (0 to 2n – 1)
• The largest number that can be stored in the counter = 2n – 1

To construct a counter with any MOD number, the minimum number flip flops required must satisfy:

Modulus ≤ 2n

Where n is the number of flip-flops and is the minimum value satisfying the above condition.

Note: A MOD-N counter is also called a divide by N counter as the input frequency is divided by the number of states of the counter.

Calculation:

Number no. of flip – flops are required to construct mod-60 counter, must satisfy:

2n ≥  60

The minimum value of n satisfying the above is:

n = 6 bits

The correct answer is Register

Key Points

• A sequential circuit is a type of logic circuit whose output depends not only on the present inputs but also on the history of inputs.
• Registers in digital logic circuits use flip-flops, which are sequential circuits because they store and process data linearly following a time sequence (clock cycles).

Additional Information

• This distinguishes them from combinational circuits such as binary adders, decoders, and multiplexers, whose outputs depend only on the current input values.
• Decoder: A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2ⁿ unique output lines. It is used to perform a variety of tasks such as data demultiplexing, memory address decoding, etc. Its output at any instant only depends on what it is currently being fed as input, it does not have a memory of past inputs.
• Binary Adder: A binary adder is another type of combinational circuit that performs the arithmetic operation of addition on binary numbers. The simplest kind of binary adder is the half adder, which adds two single binary digits. For multiple bit addition, full adders are used. Like a decoder, an adder doesn't keep track of input history - it just adds the binary numbers presented to it at any given instant.
• Multiplexer (MUX): A multiplexer is a device that takes multiple inputs and, based on a selection line(s), forwards the selected input into a single line. It is a combinational circuit because its output only depends on the current inputs and the selector line(s), not on any of the previous states of inputs.

Concept:

D flip-flop

These flip-flops are mainly used for input synchronization, counters, and shift registers.

The truth table of this flip-flop is shown below:

The characteristic equation is:

Q(t + 1) = D

Calculation:

From the given circuit the input for the flip-flop A, B, C are:

\({D_A} = {Q_B}{Q_C} + \overline {{Q_B}} \;\overline {{Q_C}} = {Q_B} \odot {Q_C}\)

D_B = Q_A

D_C = Q_B

The below table shows the transitions of all inputs based on the truth table and the given circuit configuration:

The counting sequence at Q_A = 0110100 ⋯

• MOD-2 counter followed by MOD-5 it denotes cascading of two counters. Therefore, equivalent counter = MOD (2 × 5) counter = MOD-10 counter
• MOD-10 counter is also called as BCD counter or Decade counter with ten states in its sequence.
• Hence the number of states when a MOD-2 counter is followed by a MOD-5 counter is 10

let Initial states be Q₁ = Q₂ = 0

\({D_1} = \begin{array}{*{20}{c}} {\overline {{Q_1}} }&{\overline {{Q_2}} } \end{array}\)

D₂ = Q₁

Hence after 3 clock pulses, the output repeats

It is mod – 3 counter

out frequency \(= \frac{{12}}{3} = 4\) kHz.

Concept:

The total number of states in a counter with n-flip-flops = 2ⁿ

In a Mod-m counter, the total number of states used = m

If a Mod-m counter is realized using n number, the number of states unused or number of counts that counter will skip = Total number of states – total number of states used

= 2ⁿ – m

Calculation:

Modulus of the counter (m) = 6

Number of flip-flops (n) = 3

Given counter is 

The same clock pulse is given to both the flip-flops, therefore it is synchronous counter.

For every four cycles, the output is repeated 

So, dividing 333 by 4, we get 83.25

So, at 332 (83 × 4 = 332) clock pulse the output will be 0 0 (Q₁Q₀) 

At 333^rd clock pulse, Q₁ Q₀ = 0 1

D_A = Q_C, D_B = Q_A, D_C = Q_B

\(D_A' = \bar Q_C',{\rm{\;}}D_B' = \bar Q_A',{\rm{\;}}D_C' = \bar Q_B'\)

\(Z = \left( {{Q_A} \oplus Q_A'} \right) + \left( {{Q_B} \oplus Q_B'} \right) + \left( {{Q_C} \oplus Q_C'} \right)\;\)

Z becomes zero when all the inputs of OR gates are zero

\(\Rightarrow {Q_A} \oplus Q_A' + {Q_B} \oplus Q_B' + {Q_C} \oplus Q_C' = 0\)

\(\Rightarrow {Q_A} = Q_A',{Q_B} = Q_B',{Q_C} = Q_C'\)

At 6^th clock pulse

\({Q_A}{Q_B}{Q_C} = Q_A'Q_B'Q_C' = 100\)