J-K Flip Flop MCQ Quiz in తెలుగు - Objective Question with Answer for J-K Flip Flop - ముఫ్త్ [PDF] డౌన్లోడ్ కరెన్
Last updated on Mar 29, 2025
Latest J-K Flip Flop MCQ Objective Questions
Top J-K Flip Flop MCQ Objective Questions
J-K Flip Flop Question 1:
The frequency of the output is ------------ MHz. (fCLK = 3MHz)
Answer (Detailed Solution Below) 0.0
J-K Flip Flop Question 1 Detailed Solution
The present state – Next state and the excitation table of the Flip – Flop circuit is as follows–
So the frequency is zero.
J-K Flip Flop Question 2:
The output Qn of a J-K flip-flop is zero. It changes to 1 when a clock pulse is applied. The input Jn and Kn are respectively (X represents don’t care condition):
Answer (Detailed Solution Below)
J-K Flip Flop Question 2 Detailed Solution
The excitation table for JK Flip Flop is given by,
When the previous output of J-K flip flop is 0 and then changes to 1, the input of J-K flip flop must be 1 and X.
A JK flip flop is somewhat similar to an SR flip flop.
The difference in JK and SR flip flop is that in JK flip flop condition when S=R =1 is also included. When both J=K =1 then flip flop is said to be in toggle mode. Input J and K behave like S and R to set and reset respectively.
The truth table for J K flip flop is :
| J | K | Qn |
| 0 | 0 | Q |
| 1 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 1 | Toggle |
J-K Flip Flop Question 3:
In the following digital circuit the worst case delay of FFs is 40 nsec and the AND gate has delay of 20 nsec. The maximum clock frequency of the circuit to operate is ____
Answer (Detailed Solution Below)
J-K Flip Flop Question 3 Detailed Solution
The longest path is
- 1st FF + 2nd FF + and gate + 3rd FF
thus the worst case delay = 40 + 40 + 20 + 40 = 140 nsec
Maximum clock frequency,
J-K Flip Flop Question 4:
The output Qn of a JK flip-flop is zero. It changes to 1 when a clock pulse is applied. The input Jn and Kn are respectively
Answer (Detailed Solution Below)
J-K Flip Flop Question 4 Detailed Solution
Characteristic Table of JK flip flop is:
|
J |
K |
Qn |
Qn+1 |
|
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
1 |
|
0 |
1 |
0 |
0 |
|
0 |
1 |
1 |
0 |
|
1 |
0 |
0 |
1 |
|
1 |
0 |
1 |
1 |
|
1 |
1 |
0 |
1 |
|
1 |
1 |
1 |
0 |
Qn+1 = JQ̅n + K̅Qn
Based on the table we can see the correct input combination is 1 0 and 1 1.
∴ Option 1 is correct.
J-K Flip Flop Question 5:
In the following sequential circuit the initial state (before the first clock pulse) of the circuit (Q1, Q0) = 00. The state Q1, Q0, immediately after the 334th clock pulse is
Answer (Detailed Solution Below)
J-K Flip Flop Question 5 Detailed Solution
Initial state is Q1, Q0 = 00
|
J1(Q0) |
K1(Q̅0) |
J0(Q̅1) |
K0(Q1) |
Q1 |
Q0 |
|
|
|
|
|
0 |
0 |
|
0 |
1 |
1 |
0 |
0 |
1 |
|
1 |
0 |
1 |
0 |
1 |
1 |
|
1 |
0 |
0 |
1 |
1 |
0 |
|
0 |
1 |
0 |
1 |
0 |
0 |
Given circuit is Johnson (MOD – 4) counter after 332 clock pulse we have
Q1 Q0 = (0, 0)
∴ After 334 clock pulse we have
Q1 Q0 = (1, 1)
J-K Flip Flop Question 6:
Find the output frequency ‘fo’ (in KHz) of the following sequential circuit if input frequency is 100 KHz
Answer (Detailed Solution Below) 25
J-K Flip Flop Question 6 Detailed Solution
The output frequency of toggle J-K Flip Flop is:
Again the T – Flip Flop divides the clock frequency by 2.
Hence:
Note: We can also check the modulus of the counter. Since this is a MOD 4 counter, the output frequency will be divided by 4.
J-K Flip Flop Question 7:
The digital circuit shown in figure generates a modified clock pulse at the output. Choose the correct output waveform from the options given below.
Answer (Detailed Solution Below)
J-K Flip Flop Question 7 Detailed Solution
JK – FF is in Toggle mode, hence its output frequency is half of the clock frequency.
J-K Flip Flop Question 8:
What is represented by the digital circuit given above:
Answer (Detailed Solution Below)
An JK flip – flop with A = J and B = K
J-K Flip Flop Question 8 Detailed Solution
For T. FF ⇒ Q(t+1) = T ⊕ Q
But
J-K Flip Flop Question 9:
The flip-flop behaves as a:
Answer (Detailed Solution Below)
J-K Flip Flop Question 9 Detailed Solution
Explanation:
Flip-Flop Behavior:
Definition: A flip-flop is a basic digital memory circuit used to store a single binary value. It is a bistable multivibrator, meaning it has two stable states. Flip-flops are fundamental building blocks in digital electronics and are extensively used in sequential logic circuits, registers, counters, and memory devices. The type of flip-flop determines its behavior and how it handles the input signals to transition between states.
Correct Option Analysis:
The correct option is:
Option 4: T Flip-Flop
The T flip-flop, also known as the toggle flip-flop, is a type of flip-flop that toggles its output state whenever a triggering signal (clock pulse) is applied. The behavior of the T flip-flop can be described as follows:
- Operation: The T flip-flop has a single input labeled "T" (Toggle). If T = 1, the flip-flop toggles its current state (from 0 to 1 or 1 to 0) on the rising edge of the clock pulse. If T = 0, the state remains unchanged.
- Truth Table:
Clock T Q (Current State) Qnext (Next State) ↑ 0 0 0 ↑ 0 1 1 ↑ 1 0 1 ↑ 1 1 0 - Behavior: The T flip-flop is widely used in applications like counters and toggling circuits because of its ability to change states with each clock pulse when T = 1.
Applications:
- Used in binary counters to divide the clock frequency.
- Employed in toggle switches for state-changing operations.
- Utilized in frequency division circuits.
Additional Information
To further understand the analysis, let’s evaluate the other options:
Option 1: JK Flip-Flop
The JK flip-flop is a versatile flip-flop with two inputs, J and K. It behaves differently based on the combination of its inputs:
- J = 0, K = 0: No change in state.
- J = 0, K = 1: Reset the output to 0.
- J = 1, K = 0: Set the output to 1.
- J = 1, K = 1: Toggle the output state.
While the JK flip-flop can toggle like the T flip-flop, it requires both inputs to be active (J = 1, K = 1) for toggling. Therefore, it is not specifically defined as a T flip-flop.
Option 2: RS Flip-Flop
The RS (Reset-Set) flip-flop is one of the simplest types of flip-flops. It has two inputs, R and S:
- R = 0, S = 0: No change in state.
- R = 0, S = 1: Set the output to 1.
- R = 1, S = 0: Reset the output to 0.
- R = 1, S = 1: Undefined state (not allowed).
This flip-flop does not toggle its state based on a single input, making it different from the T flip-flop.
Option 3: D Flip-Flop
The D (Data) flip-flop is designed to store a single bit of data. It has one input, D:
- D = 0: The output is reset to 0 on the clock pulse.
- D = 1: The output is set to 1 on the clock pulse.
The D flip-flop simply transfers the input to the output on the clock edge, without any toggling behavior, unlike the T flip-flop.
Option 5: This option is irrelevant to the context provided.
Conclusion:
Among the given choices, the T flip-flop (Option 4) is the correct answer because it specifically toggles its output state on the clock pulse, matching the described behavior. Understanding the distinctions between different types of flip-flops is essential for selecting the appropriate type for specific applications in digital circuit design.
J-K Flip Flop Question 10:
The output Qn of a J-K flip-flop is zero. It changes to 1 when a clock pulse is applied. The input Jn and Kn are respectively (X represents don’t care condition):
Answer (Detailed Solution Below)
J-K Flip Flop Question 10 Detailed Solution
The excitation table for JK Flip Flop is given by,
When the previous output of J-K flip flop is 0 and then changes to 1, the input of J-K flip flop must be 1 and X.
A JK flip flop is somewhat similar to an SR flip flop.
The difference in JK and SR flip flop is that in JK flip flop condition when S=R =1 is also included. When both J=K =1 then flip flop is said to be in toggle mode. Input J and K behave like S and R to set and reset respectively.
The truth table for J K flip flop is :
| J | K | Qn |
| 0 | 0 | Q |
| 1 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 1 | Toggle |